I have a 9205 analog input module in a 9068 cRIO chassis. I understand that I must sample all the analog channels at a common rate. However, this means that the lower bandwidth channels will be highly oversampled in order to avoid aliasing of the higher bandwidth ones. Rather than flood our logging system with all this oversampled data, I would like to insert resampling filters in the lower bandwidth digital signal paths. It would be straightforward to do this in software but there will likely be performance limitations. Alternatively, is this something that can be implemented in the cRIO FPGA? I know that's the sort of thing the FPGA was intended for but it's not clear to me if I can implement channel-specific filters.