Usage of external reference clock input (refclk) and PLL with X-Series (PXIe6363)

I would like to use the PXIe 6363 DAQmx card to generate two analog signals.

To be in phase and to avoid drift with other external topics it is required to use the

external reference clock input at PFI<0..15> with a signal freq. of app. 15 kHz.

Belonging to X Series User Manual, chapter 9: Digital Routing and clock generation
Input of PLL: external reference clock: PFI<0..15> this should be possibel.

In classical PLLs designs the divider settings (pre-divider, post-divider and mainly the feedback-divider)

are know / programmable by the user for generating the requested output frequency.

Since the documentation is currently not clear to me:
1. Does this work with an input frequency of 15 kHz (specified input frequency range of PLL?)

2. What will be the output frequency of the PLL / programming of feedback devider settings of the PLL?

Thanks and best regards,

Andreas